Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. Birgitta Böckeler, Distinguished Engineer at ...

Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. Martin Kleppmann, an associate professor at ...

JTAG has its place but it is not by any means the total solution. Boundary scan, as standardized by IEEE 1149.1 and commonly referred to as JTAG, has truly revolutionized the testability of circuit ...

The emergence of SoC has been described as a development that will require fundamental changes in the approaches to design-for -testability (DFT). This will take the form of a "test re-use" strategy ...

Before you get into the details of a design, you can use a general technique to locate places at which added test points or components can increase testability. First, draw a diagram that includes the ...

For much of the lifetime of digital IC engineering, testability has been one of those issues that was somebody else's problem. But with the arrival of the SoC, it has become clear that testability ...

Software has typically been developed with three primary considerations in mind: time to market, budget and functionality. The schedule rules, now more than ever; software has become a competitive ...

Atrenta's SpyGlass DFT, an addition to its SpyGlass predictive-analysis tool, helps designers identify at the register transfer level (RTL) testability issues that would normally appear only at the ...