GitHub

sv2v: SystemVerilog to Verilog

sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs. The primary goal of this project is to create a completely ...
Design-Reuse

Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach

In today’s fast-paced silicon industry, hardware design is under constant pressure to innovate, iterate, and ship faster. Traditional Register Transfer Level (RTL) design processes—though foundational ...
IEEE

Vending Machine Using Verilog (FPGA)

Abstract: The design and implementation of a vending machine system using Verilog HDL on an FPGA board. The vending machine is equipped with multiple states including product selection, amount ...
acm.org

Nand to Tetris: Building a Modern Computer System from First Principles

Suppose you were asked to design an abridged computer science (CS) program consisting of just three courses. How would you go about it? The first course would probably be an introduction to computer ...
IEEE

A Compact Modeling Methodology for Experimental Memristive Devices

Abstract: A methodology to create and develop electrical compact models for memristive devices is presented. It comprises a six-step algorithm that uses experimental data of memristive devices in ...
acm.org

Deriving Equations from Sensor Data Using Dimensional Function Synthesis

We present a new method for deriving functions that model the relationship between multiple signals in a physical system. The method, which we call dimensional function synthesis, applies to data ...
Design-Reuse

System Verilog Macro: A Powerful Feature for Design Verification Projects

For any design verification (DV) project, following best coding practices make life easier for the teammates. On the other hand, bad coding style leads to a lot of issues when the code is reused, or ...