IEEE

Verilog Code Generation of Hierarchical Design Using LLMs

Abstract: Creating RTL hierarchy and generating module-by-module Verilog code, both through a large language model (LLM), are presented. (1) For RTL hierarchy, LLM is prompted to identify a list of ...
Hackaday

PJON, Open Single-Wire Bus Protocol, Goes Verilog

Did OneWire of DS18B20 sensor fame ever fascinate you in its single-data-line simplicity? If so, then you’ll like PJON (Padded Jittering Operative Network) – a single-wire-compatible protocol for up ...
Design-Reuse

Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach

In today’s fast-paced silicon industry, hardware design is under constant pressure to innovate, iterate, and ship faster. Traditional Register Transfer Level (RTL) design processes—though foundational ...
elektormagazine

Learn FPGAs and Verilog with Elektor Academy Pro

Explore FPGA development using Verilog with this complete kit from Elektor Academy Pro, including hardware, structured learning and practical signal processing projects. Discover an exciting new ...
Semiconductor Engineering

Largest High-Quality Verilog Dataset for LLM Fine-Tuning (Univ. of Florida)

A new technical paper titled “VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation” was published by researchers at the University of Florida.
IEEE

GEMMV: An LLM-Based Automated Performance-Aware Framework for GEMM Verilog Generation

Abstract: Recent advancements in artificial intelligence (AI) models have intensified the need for specialized AI accelerators. The design of optimized general matrix multiplication (GEMM) module ...
GitHub

Verilog Package Manager (VPM)

VPM is a powerful package manager for Verilog projects, currently being piloted at Stanford and UC Berkeley. It's designed to streamline the management, reuse, and communication of IP cores and ...