IEEE

Implementation of 128-bit Radix-4 Booth Multiplier

Abstract: A description of the multiplication of two binary numbers of size 128-bits each using Radix-4 Booth's Algorithm is presented in this paper. Booth Encoder circuit, Partial Product Generator ...
IEEE

Implementation of radix 4 booth multiplier using MGDI technique

Abstract: Here we presents Modified Gate Diffusion Input technique used to implement radix 4 Booth Multiplier. Use of Booth algorithm as compare to other multiplication algorithms in multiplication ...
Europe PMC

Resource-Efficient Optimization for FPGA-Based Convolution Accelerator

Convolution forms one of the most essential operations for the FPGA-based hardware accelerator. However, the existing designs often neglect the inherent architecture of FPGA, which puts forward an ...
GitHub

floating-point-multiplier

⚡This project aims to implement 6 different multipliers including the radix-4 booth multiplier, a multiplier tree, floating-point multiplier and more.. in verilog as well as synthesize each one on ...
Scientific Research Publishing

A New Clock Gated Flip Flop for Pipelining Architecture ()

The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock ...
Europe PMC

Extending the IEEE 802.15.4 security suite with a compact implementation of the NIST P-192/B-163 elliptic curves.

Typically, commercial sensor nodes are equipped with MCUsclocked at a low-frequency (i.e., within the 4-12 MHz range). Consequently, executing cryptographic algorithms in those MCUs generally requires ...